Model {
  Name			  "v34cod32"
  Version		  4.00
  SampleTimeColors	  off
  LibraryLinkDisplay	  "none"
  WideLines		  off
  ShowLineDimensions	  off
  ShowPortDataTypes	  off
  RecordCoverage	  off
  CovPath		  "/"
  CovSaveName		  "covdata"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  BlockNameDataTip	  off
  BlockParametersDataTip  on
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks off
  BrowserLookUnderMasks	  off
  Created		  "Tue Oct 20 09:11:53 1998"
  Creator		  "tdelve"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "ysong"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Wed Aug 23 12:01:31 2000"
  ModelVersionFormat	  "1.%<AutoIncrement:7>"
  ConfigurationManager	  "none"
  SimParamPage		  "Solver"
  StartTime		  "0.0"
  StopTime		  "999999"
  SolverMode		  "SingleTasking"
  Solver		  "VariableStepDiscrete"
  RelTol		  "1e-3"
  AbsTol		  "1e-6"
  Refine		  "1"
  MaxStep		  "auto"
  MinStep		  "auto"
  MaxNumMinSteps	  "-1"
  InitialStep		  "auto"
  FixedStep		  "auto"
  MaxOrder		  5
  OutputOption		  "RefineOutputTimes"
  OutputTimes		  "[]"
  LoadExternalInput	  off
  ExternalInput		  "[t, u]"
  SaveTime		  off
  TimeSaveName		  "tout"
  SaveState		  off
  StateSaveName		  "xout"
  SaveOutput		  off
  OutputSaveName	  "yout"
  LoadInitialState	  off
  InitialState		  "xInitial"
  SaveFinalState	  off
  FinalStateName	  "xFinal"
  SaveFormat		  "Array"
  LimitDataPoints	  off
  MaxDataPoints		  "1000"
  Decimation		  "1"
  AlgebraicLoopMsg	  "warning"
  MinStepSizeMsg	  "warning"
  UnconnectedInputMsg	  "warning"
  UnconnectedOutputMsg	  "warning"
  UnconnectedLineMsg	  "warning"
  InheritedTsInSrcMsg	  "warning"
  SingleTaskRateTransMsg  "none"
  MultiTaskRateTransMsg	  "error"
  IntegerOverflowMsg	  "warning"
  CheckForMatrixSingularity "none"
  UnnecessaryDatatypeConvMsg "none"
  Int32ToFloatConvMsg	  "warning"
  SignalLabelMismatchMsg  "none"
  LinearizationMsg	  "none"
  VectorMatrixConversionMsg "none"
  SfunCompatibilityCheckMsg "none"
  BlockPriorityViolationMsg "warning"
  ArrayBoundsChecking	  "none"
  ConsistencyChecking	  "none"
  ZeroCross		  on
  Profile		  off
  SimulationMode	  "normal"
  RTWSystemTargetFile	  "grt.tlc"
  RTWInlineParameters	  off
  RTWRetainRTWFile	  off
  RTWTemplateMakefile	  "grt_default_tmf"
  RTWMakeCommand	  "make_rtw"
  RTWGenerateCodeOnly	  off
  TLCProfiler		  off
  TLCDebug		  off
  TLCCoverage		  off
  AccelSystemTargetFile	  "accel.tlc"
  AccelTemplateMakefile	  "accel_default_tmf"
  AccelMakeCommand	  "make_rtw"
  ExtModeMexFile	  "ext_comm"
  ExtModeBatchMode	  off
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "oneshot"
  ExtModeTrigPort	  "1"
  ExtModeTrigElement	  "any"
  ExtModeTrigDuration	  1000
  ExtModeTrigHoldOff	  0
  ExtModeTrigDelay	  0
  ExtModeTrigDirection	  "rising"
  ExtModeTrigLevel	  0
  ExtModeArchiveMode	  "off"
  ExtModeAutoIncOneShot	  off
  ExtModeIncDirWhenArm	  off
  ExtModeAddSuffixToVar	  off
  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  off
  ExtModeLogAll		  on
  OptimizeBlockIOStorage  on
  BufferReuse		  on
  ParameterPooling	  on
  BlockReductionOpt	  off
  BooleanDataType	  off
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "v34cod32"
    Location		    [39, 259, 881, 532]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "usletter"
    PaperUnits		    "inches"
    ZoomFactor		    "100"
    AutoZoom		    on
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Inport
      Name		      "In1"
      Position		      [165, 25, 185, 45]
      Orientation	      "down"
      Port		      "1"
      Interpolate	      on
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
    }
    Block {
      BlockType		      Inport
      Name		      "In2"
      Position		      [115, 25, 135, 45]
      Orientation	      "down"
      ForegroundColor	      "green"
      Port		      "2"
      Interpolate	      on
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
    }
    Block {
      BlockType		      Inport
      Name		      "In3"
      Position		      [70, 25, 90, 45]
      Orientation	      "down"
      ForegroundColor	      "yellow"
      Port		      "3"
      Interpolate	      on
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
    }
    Block {
      BlockType		      Inport
      Name		      "In4"
      Position		      [25, 25, 45, 45]
      Orientation	      "down"
      ForegroundColor	      "magenta"
      Port		      "4"
      Interpolate	      on
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
    }
    Block {
      BlockType		      Logic
      Name		      "Logical\nOperator"
      Ports		      [2, 1]
      Position		      [155, 120, 190, 160]
      ForegroundColor	      "blue"
      ShowName		      off
      Operator		      "XOR"
      Inputs		      "2"
    }
    Block {
      BlockType		      Logic
      Name		      "Logical\nOperator1"
      Ports		      [2, 1]
      Position		      [315, 120, 350, 160]
      ForegroundColor	      "blue"
      ShowName		      off
      Operator		      "XOR"
      Inputs		      "2"
    }
    Block {
      BlockType		      Logic
      Name		      "Logical\nOperator2"
      Ports		      [2, 1]
      Position		      [455, 120, 490, 160]
      ForegroundColor	      "blue"
      ShowName		      off
      Operator		      "XOR"
      Inputs		      "2"
    }
    Block {
      BlockType		      Logic
      Name		      "Logical\nOperator3"
      Ports		      [2, 1]
      Position		      [615, 120, 650, 160]
      ForegroundColor	      "blue"
      ShowName		      off
      Operator		      "XOR"
      Inputs		      "2"
    }
    Block {
      BlockType		      Memory
      Name		      "Memory"
      Position		      [65, 120, 105, 150]
      ForegroundColor	      "red"
      ShowName		      off
      X0		      "0"
      InheritSampleTime	      off
    }
    Block {
      BlockType		      Memory
      Name		      "Memory1"
      Position		      [230, 125, 270, 155]
      ForegroundColor	      "red"
      ShowName		      off
      X0		      "0"
      InheritSampleTime	      off
    }
    Block {
      BlockType		      Memory
      Name		      "Memory2"
      Position		      [380, 125, 420, 155]
      ForegroundColor	      "red"
      ShowName		      off
      X0		      "0"
      InheritSampleTime	      off
    }
    Block {
      BlockType		      Memory
      Name		      "Memory3"
      Position		      [525, 125, 565, 155]
      ForegroundColor	      "red"
      ShowName		      off
      X0		      "0"
      InheritSampleTime	      off
    }
    Block {
      BlockType		      Memory
      Name		      "Memory4"
      Position		      [685, 125, 725, 155]
      ForegroundColor	      "red"
      ShowName		      off
      X0		      "0"
      InheritSampleTime	      off
    }
    Block {
      BlockType		      Outport
      Name		      "Out1"
      Position		      [610, 50, 630, 70]
      NamePlacement	      "alternate"
      Port		      "1"
      OutputWhenDisabled      "held"
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "Out2"
      Position		      [660, 65, 680, 85]
      NamePlacement	      "alternate"
      Port		      "2"
      OutputWhenDisabled      "held"
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "Out3"
      Position		      [710, 80, 730, 100]
      NamePlacement	      "alternate"
      Port		      "3"
      OutputWhenDisabled      "held"
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "Out4"
      Position		      [755, 95, 775, 115]
      NamePlacement	      "alternate"
      Port		      "4"
      OutputWhenDisabled      "held"
      InitialOutput	      "0"
    }
    Block {
      BlockType		      Outport
      Name		      "Out5"
      Position		      [800, 130, 820, 150]
      NamePlacement	      "alternate"
      Port		      "5"
      OutputWhenDisabled      "held"
      InitialOutput	      "0"
    }
    Line {
      SrcBlock		      "In2"
      SrcPort		      1
      Points		      [0, 25; 0, 0]
      Branch {
	Points			[0, 55]
	DstBlock		"Logical\nOperator"
	DstPort			1
      }
      Branch {
	Points			[470, 0]
	Branch {
	  Points		  [0, 55]
	  DstBlock		  "Logical\nOperator3"
	  DstPort		  1
	}
	Branch {
	  DstBlock		  "Out2"
	  DstPort		  1
	}
      }
    }
    Line {
      SrcBlock		      "In1"
      SrcPort		      1
      Points		      [0, 10; 115, 0]
      Branch {
	Points			[0, 70]
	DstBlock		"Logical\nOperator1"
	DstPort			1
      }
      Branch {
	DstBlock		"Out1"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "In4"
      SrcPort		      1
      Points		      [0, 55; 400, 0]
      Branch {
	Points			[0, 25]
	DstBlock		"Logical\nOperator2"
	DstPort			1
      }
      Branch {
	DstBlock		"Out4"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Memory4"
      SrcPort		      1
      Points		      [10, 0; 0, 0]
      Branch {
	DstBlock		"Out5"
	DstPort			1
      }
      Branch {
	Points			[0, 40; -695, 0; 0, -45]
	DstBlock		"Memory"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "Memory3"
      SrcPort		      1
      Points		      [15, 0; 0, 10]
      DstBlock		      "Logical\nOperator3"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Memory1"
      SrcPort		      1
      Points		      [15, 0; 0, 10]
      DstBlock		      "Logical\nOperator1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Memory2"
      SrcPort		      1
      Points		      [5, 0; 0, 10]
      DstBlock		      "Logical\nOperator2"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Logical\nOperator3"
      SrcPort		      1
      DstBlock		      "Memory4"
      DstPort		      1
    }
    Line {
      SrcBlock		      "In3"
      SrcPort		      1
      Points		      [0, 40]
      DstBlock		      "Out3"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Memory"
      SrcPort		      1
      Points		      [15, 0; 0, 15]
      DstBlock		      "Logical\nOperator"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Logical\nOperator"
      SrcPort		      1
      DstBlock		      "Memory1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Logical\nOperator1"
      SrcPort		      1
      DstBlock		      "Memory2"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Logical\nOperator2"
      SrcPort		      1
      DstBlock		      "Memory3"
      DstPort		      1
    }
    Annotation {
      Position		      [407, 192]
      VerticalAlignment	      "top"
      Text		      "V.34 32 state convolution encoder"
    }
    Annotation {
      Position		      [400, 252]
      Text		      "Warning: This model is obsolete and may be remo"
"ved in the future."
      FontName		      "Arial"
      FontSize		      12
    }
  }
}